The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having improved operational speed with application of stress and a fabrication method of such a semiconductor device.
With progress in the art of device miniaturization, it is now becoming possible to realize ultrafine and ultra fast semiconductor devices having a gate length of 100 nm or less.
With such ultrafine and ultra fast transistors, the area of the channel region right underneath the gate electrode is much smaller than conventional semiconductor devices, and thus, the mobility of electrons or holes traveling through the channel region is influenced heavily by the stress applied to such a channel region.
Thus, various attempts have been made for optimizing the stress applied to the channel region in the prospect of improving the operational speed of the semiconductor device further.
In semiconductor devices that use a silicon substrate as a channel region, the mobility of holes is generally smaller than the mobility of electrons, and thus, it is particularly important to improve the operational speed of p-channel MOS transistors, in which holes are used for the carriers, in the designing of semiconductor integrated circuits.
With such p-channel MOS transistors, it is known that the mobility of carriers is improved by applying a uniaxial compressive stress to the channel region, and there is a proposal to use the construction of FIG. 1 as the means of applying the compressive stress to the channel region.
Referring to FIG. 1, there is formed a gate electrode 3 on a silicon substrate 1 via a gate insulation film 2, and p-type diffusion regions 1a and 1b are formed in the silicon substrate 1 at both lateral sides of the gate electrode 3 so as to define the channel region. Further, sidewall insulation films 3A and 3B are formed on the sidewall surfaces of the gate electrode 3 so as to cover also a surface part of the silicon substrate 1.
Thereby, the diffusion regions 1a and 1b function respectively as a source extension region and a drain extension region of the MOS transistor, and the flow of the holes transported through the channel region right underneath the gate electrode 3 from the diffusion region 1a to the diffusion region 1b is controlled by the gate voltage applied to the gate electrode 3.
Further, there are formed SiGe mixed crystal regions 1A and 1B in the silicon substrate 1 in the construction of FIG. 1 at respective outer sides of the sidewall insulation films 3A and 3B with epitaxial relationship with the silicon substrate 1, and p-type source 1c and drain 1d regions are formed in the SiGe mixed crystal regions 1A and 1B respectively in continuation from the diffusion region 1 a and the diffusion region 1b. 
Because the SiGe mixed crystal regions 1A and 1B have a lattice constant larger than that of the silicon substrate 1 in the MOS transistor of the construction of FIG. 1, the SiGe mixed crystal regions 1A and 1B are applied with a compressive stress as shown in FIG. 1 by an arrow a, and as a result, the SiGe mixed crystal regions 1A and 1B undergo deformation in the direction generally perpendicular to the surface of the silicon substrate 1 as shown by an arrow b.
Because the SiGe mixed crystal regions 1A and 1B are thus formed epitaxially on the silicon substrate 1, such a deformation of the SiGe mixed crystal regions 1A and 1B represented by the arrow b induces a corresponding deformation in the channel region of the silicon substrate as represented by an arrow c, while such a deformation in the channel region induces a uniaxial compressive stress in the channel region as represented by an arrow d.
As a result of such a uniaxial compressive stress applied to the channel region of the MOS transistor of FIG. 1, the symmetry of the Si crystal constituting the channel region is locally modulated, and as a result of such local modulation of the symmetry, degeneration of heavy holes and light holes in the valence band is resolved. Thereby, there is caused increase of hole mobility in the channel region, leading to improvement of operational speed of the transistor.
It should be noted that such increase of hole mobility caused in the channel region by locally induced stress appears particularly conspicuously in the ultrafine semiconductor devices having a gate length of 100 nm or less.
FIG. 2 shows the construction of a p-channel MOS transistor based on such a principle and described in Non-Patent Reference 1. In the drawing, those parts corresponding to the parts described previously are designated by the same reference numerals and the description thereof will be omitted.
Referring to FIG. 2, the SiGe mixed crystal regions 1A and 1B are formed epitaxially so as to fill the respective trenches formed in the silicon substrate 1 up to the level higher than the interface between the silicon substrate 1 and the gate electrode 2 represented in the drawing by a dotted line L, Further, it should be noted that the mutually facing side surfaces 1As and 1Bs of the SiGe mixed crystal regions 1A and 1B are formed to have a curved shape such that the distance between the SiGe mixed crystal regions 1A and 1B increases continuously in the downward direction of the silicon substrate 1 from the lower surface of the gate insulation film 2.
Further, in the conventional construction of FIG. 2 in which the SiGe mixed crystal regions 1A and 1B grown to the level higher than the foregoing level L are formed directly with a silicide layer 4. A similar silicide layer 4 is formed also on the polysilicon gate electrode 3.